About Me
Blog with some technical notes: https://pcotret.gitlab.io/blog/
Interests
- Embedded systems
- Security
- Hardware/software co-design
- Microarchitecture
Education
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PhD in embedded security
Université de Bretagne-Sud
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MEng Optoelectronic
Télécom Saint-Etienne
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BEng Computer Science
University of South Wales
📚 My Research
🔭 I’m currently working on CVA6 and other RISC-V cores and low-level security (involving software and hardware)
🌱 Micro-architectural issues (cache-based attacks, Trusted Execution Environments), trace mechanisms in embedded processors and VMs (JIT and so on)
Please reach out to collaborate 😃
Recent Publications
(2025).
Enforcing RISC-V TEE Security Against Cache Timing Attacks.
In Cryptarchi.
(2025).
Security of Dynamically Reconfigurable RISC-V Systems: I/O Attack Focus.
In 32nd RAW.
(2025).
Support matériel pour la distribution de moteurs IA embarqués.
In 2ème conférence française annuelle dédiée à la cyber embarquée et à son écosystème (CyberOnBoard 2025).
(2025).
War on JITs: Software-Based Attacks and Hybrid Defenses for JIT Compilers - A Comprehensive Survey.
In ACM Computing Surveys.
(2024).
A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking.
In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024.