Biography
Blog with some technical notes: https://pcotret.gitlab.io/blog/
Opened positions
- Internship about TEE and RISC-V processor (spring/summer 2025) : Implementation of a TEE on a RISC-V embedded processor
Interests
- Embedded systems
- Security/cryptography
- Reconfigurable architectures
Education
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PhD in embedded security, 2012
Université de Bretagne-Sud
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MEng in optoelectronics, 2009
Télécom Saint-Etienne
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BSc in computer science, 2008
University of Glamorgan
Latest publications
(2024).
Cache locking against cache-based side-channel attacks.
In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024.
(2024).
On The Effect of Replacement Policies on The Security of Randomized Cache Architectures.
In 19th ACM ASIA Conference on Computer and Communications Security (ACM AsiaCCS 2024).
(2024).
Enhancing Security in Heterogeneous Virtualized Systems: A Focus on I/O Attacks in the existence of IOMMU in a RISC-V architecture.
In GDR SoC².
(2024).
RISC-V Embedded AI for IDS Applications.
In RESSI 2024 Rendez-vous de la Recherche et de l’Enseignement de la Sécurité des Systèmes d’Information.
(2024).
Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cache.
In 1ère conférence française annuelle dédiée à la cyber embarquée et à son écosystème (CyberOnBoard 2024).
Research
Teaching
Engineering degree - Associate professor
Network basics, security & networks
Apprentice degree - Associate professor and responsible of this degree
Embedded C and OS, network basics