Software Mitigations for Cache and Covert Timing SCAs
Since 2024 · Co-supervised with Vianney Lapôtre, Loïc Lagadec
Software Mitigations for Cache and Covert Timing SCAs.
RISC-V and IOMMU
Since 2023 · Co-supervised with Philippe Tanguy, Jean-Christophe Prévotet
RISC-V and IOMMU.
Embedded IDS for RISC-V targeting drone systems
Since 2023 · Co-supervised with Loïc Lagadec, Jean-Christophe Cexus, Julien Francq
Embedded IDS for RISC-V targeting drone systems.
Security mechanisms against timing cache attacks
2021–2024 · Co-supervised with Vianney Lapôtre, Guy Gogniat
Now: Engineer at SEALSQ
Security mechanisms against timing cache attacks.
Low-level JIT security mechanisms for VMs running on RISC-V processors
2020–2024 · Co-supervised with Loïc Lagadec
Now: Postdoc at INRIA SUSHI
Low-level JIT security mechanisms for VMs running on RISC-V processors.
2015–2020 · Co-supervised with Guillaume Hiet
Now: Co-founder & CTO at Fabor
HardBlare - Information flow tracking through static and dynamic analysis.
Hardware support for the security analysis of embedded softwares : applications on information flow control and malware analysis
2015–2018 · Co-supervised with Christophe Moy, Guillaume Hiet, Vianney Lapôtre
Now: Engineer at Siemens
Hardware support for the security analysis of embedded softwares : applications on information flow control and malware analysis.
