Here are a selection of projects that I have worked on over the years.
Ensure by construction that a security sensitive code is immune to timing side-channel attacks, focusing RISC-V.
Work on the RISC-V ISA, extending it for the security of language VMs.
Propose an heterogeneous solution for embedded software security. Relies on ARM debug components.
Full list
Current students Oussama Elmnaouri. 2024-present. Software Mitigations for Cache and Covert Timing SCAs. Supervised with Vianney Lapôtre and Loïc Lagadec. Pierre Garreau. 2023-present. Embedded IDS for RISC-V targeting drone systems. Supervised with Loïc Lagadec and Jean-Christophe Cexus. Aya Jendoubi. 2023-present. RISC-V and IOMMU. Supervised with Philippe Tanguy and Jean-Christophe Prévotet. Past students Nicolas Gaudin. 2021-2024, now engineer at Trasna. Security mechanisms against timing cache attacks. Supervised with Vianney Lapôtre and Guy Gogniat. Quentin Ducasse. 2020-2024, now postdoc at INRIA SUSHI. Low-level JIT security mechanisms for VMs running on RISC-V processors. Supervised with Loïc Lagadec. Mounir Nasr Allah. 2015-2020, now CTO at Fabor. HardBlare - Information flow tracking through static and dynamic analysis. Supervised with Guillaume Hiet. Muhammad Abdul Wahab. 2015-2018, now engineer at Siemens. Hardware support for the security analysis of embedded softwares : applications on information flow control and malware analysis. Supervised with Guillaume Hiet.
SCAMA (2024 - …) Processeur sécurisé dès la conception contre les attaques microarchitecturales Funding: ANR Leading a work package Embedded IDS for RISC-V targeting drone systems (2023 - …) Embedded security, in the context of a maritime cybersecurity consortium Funding: Chaire cyberdéfense navale Supervision of a PhD student TrustGW (2021 - …) Protection de gateway IoT contre des menaces logicielles et sur les communications Funding: ANR Leading a work package SCRATCHS (2021 - …) Side-Channel Resistant Applications Through Co-designed Hardware/Software Funding: Cominlabs Co-supervision of a PhD student LVM & RISC-V (2020 - …) Security of a high-level LVM with RISC-V extensions Funding by PEC (Pôle d’Excellence Cyber) & Brest Métropole Supervision of a PhD student HardBlare (2015 - 2018) HW/SW codesign for Information flow tracking on ARM processors Funding: Cominlabs https://project.inria.fr/hardblare/
