@article{GARREAU2025103501,
title = {A survey on versatile embedded Machine Learning hardware acceleration},
journal = {Journal of Systems Architecture},
volume = {167},
pages = {103501},
year = {2025},
issn = {1383-7621},
doi = {https://doi.org/10.1016/j.sysarc.2025.103501},
url = {https://www.sciencedirect.com/science/article/pii/S1383762125001730},
author = {Pierre Garreau and Pascal Cotret and Julien Francq and Jean-Christophe Cexus and Loïc Lagadec},
keywords = {Hardware acceleration, Machine Learning, Multi-application, Embedded devices},
abstract = {This survey investigates recent developments in versatile embedded Machine Learning (ML) hardware acceleration. Various architectural approaches for efficient implementation of ML algorithms on resource-constrained devices are analyzed, focusing on three key aspects: performance optimization, embedded system considerations (throughput, latency, energy efficiency) and multi-application support. Nevertheless, it does not take into account attacks and defenses of ML architectures themselves. The survey then explores different hardware acceleration strategies, from custom RISC-V instructions to specialized Processing Elements (PEs), Processing-in-Memory (PiM) architectures and co-design approaches. Notable innovations include flexible bit-precision support, reconfigurable PEs, and optimal memory management techniques for reducing weights and (hyper)-parameters movements overhead. Subsequently, these architectures are evaluated based on the aforementioned key aspects. Our analysis shows that relevant and robust embedded ML acceleration requires careful consideration of the trade-offs between computational capability, power consumption, and architecture flexibility, depending on the application.}
}