Poster- HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments
- Priority-Aware Scheduling of Multi-Model, Multi-Precision DNN Inference on Multi-Cores RISC-V
- Security of Dynamically Reconfigurable RISC-V Systems: I/O Attack Focus
- Enhancing Keystone Security Against Cache Timing Attacks: A Modular Approach
- Enhancing Security in Heterogeneous Virtualized Systems: A Focus on I/O Attacks in the existence of IOMMU in a RISC-V architecture
- RISC-V Embedded AI for IDS Applications
- Securing a high-level language virtual machine through its ISA: Pharo as a case study
- Monitoring information flows in heterogeneous SoCs with a dedicated coprocessor
- ARMHEx: a hardware extension for information flow tracking on ARM-based platforms
- ARMHEx: a hardware extension for information flow tracking on ARM-based platforms
- A portable approach for SoC-based Dynamic Information Flow Tracking implementations
- HardBlare: an efficient hardware-assisted DIFC for non-modified embedded processors
- Reconnaissance faciale basée sur les ondelettes robuste et optimisée pour les systèmes embarqués
- Self-configuration of latency-efficient security enhancements for mpsoc communications monitoring
- Distributed security for communications and memories in a multiprocessor architecture
- Secured communications within a multi-processors architecture
- Sécurisation des communications dans une architecture multi-processeurs
