SCRATCHS
Ensure by construction that a security sensitive code is immune to timing side-channel attacks, focusing RISC-V.
Dec 18, 2024
A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking
Jul 1, 2024
Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cache
Mar 5, 2024
Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections
Jul 3, 2023