MPSoC on Pascal Cotret

Protection of heterogeneous architectures on FPGAs: an approach based on hardware firewalls

Fri, 01 Jul 2016 00:00:00 +0000

Embedded systems are parts of our daily life and used in many fields. They can be found in smartphones or in modern cars including GPS, light/rain sensors and other electronic assistance mechanisms. These systems may handle sensitive data (such as credit card numbers, critical information about the host system and so on) which must be protected against external attacks as these data may be transmitted through a communication link where attackers can connect to extract sensitive information or inject malicious code within the system. This work presents an approach to protect communications in multiprocessor architectures. This approach is based on hardware security enhancements acting as firewalls. These firewalls filter all data going through the system communication bus and an additional flexible cryptographic block aims to protect external memory from attacks. Benefits of our approach are demonstrated using a case study and some custom software applications implemented in a Field-Programmable Gate Array (FPGA). Firewalls implemented in the target architecture allow getting a low-latency security layer with flexible cryptographic features. To illustrate the benefit of such a solution, implementations are discussed for different MPSoCs implemented on Xilinx Virtex-6 FPGAs. Results demonstrate a reduction up to 33% in terms of latency overhead compared to existing efforts.

Protection des architectures hétérogènes sur FPGA : une approche par pare-feux matériels

Sat, 01 Feb 2014 00:00:00 +0000

Les systèmes embarqués font désormais partie intégrante de la vie quotidienne. Ces systèmes peuvent occasionnellement manipuler des données sensibles liées à l’utilisateur ou au système lui-même : la sécurité des données devient un paramètre important du cycle de développement. Dans le cadre de cet article, nous proposons d’illustrer une solution sécurisée d’une architecture simplifiée implémentée sur un composant reconfigurable FPGA. Les techniques proposées peuvent être utilisées dans différentes applications.

Self-reconfigurable security-enhanced communications in FPGA-based MPSoCs

Wed, 20 Jun 2012 00:00:00 +0000

Nowadays, security is a key constraint in MPSoC development lifecycle as many critical and secret information can be stored and manipulated in these systems. Monitoring and controlling communications is a method to protect an embedded system from classic attacks such as malicious accesses to restricted components. This work proposes security enhancements based on Block RAMs and AES-GCM ciphering to provide the designer an AXI-compliant design where no user intervention is required for reconfiguration of security services. A Virtex-6 FPGA implementation (with a set of miBench and custom applications) demonstrates a reduction up to 33% in terms latency overhead compared to an unprotected multiprocessor architecture and an area overhead around 10% for the reconfiguration logic.

Protecting communications in bus-based MPSoCs using hardware firewalls

Sat, 18 Jun 2011 00:00:00 +0000

The need for security in embedded systems has strongly increased since several years. Nowadays, it is possible to integrate several processors in a single chip. The design of such multiprocessor systems-on-chip (MPSoC) must be done with a lot of care as the execution of applications may lead to potential vulnerabilities such as revelation of critical data and private information. Among the critical points, protection of the communications is very sensible as most of the data are exchanged through the communication architecture of the system. This paper targets this point and proposes an efficient (in terms of latency-area trade-off) and distributed solution based on full hardware interfaces to protect AXI-based MPSoC architectures. This solution does not require software modifications and should be portable to other technologies using ARM communication standard. A case study implemented on Virtex-6 FPGAs is given in this work. The reliability of our solution is studied on larger-scale architectures using a set of benchmarks and a comparison with existing solutions.