TEE on Pascal Cotret

HermiCache: Enclave-Aware Cache Replacement for Trusted Execution Environments

Fri, 19 Jun 2026 00:00:00 +0000

Trusted Execution Environments (TEEs) protect enclave memory from untrusted software but remain vulnerable to cache-based side-channel attacks due to shared microarchitectural resources. Existing hardware defenses mainly rely on cache partitioning, which reduces effective capacity, or randomized remapping, which provides only probabilistic protection. This paper presents HermiCache, a deterministic enclave-aware cache isolation mechanism that enforces eviction confinement through ownership-aware replacement without partitioning. Each cache line is extended with lightweight metadata so that lookup and replacement decisions are restricted to the requester security domain. HermiCache is implemented at RTL in the CVA6 RISC-V core and integrated with Keystone. FPGA synthesis shows less than 5% hardware overhead, while gem5 evaluation reports up to 5% IPC degradation for secure and non-secure workloads.

Enclave-Aware Cache Replacement for Trusted Execution Environments

Thu, 05 Feb 2026 00:00:00 +0000

Presentation at this workshop.

Enforcing RISC-V TEE Security Against Cache Timing Attacks

Sun, 15 Jun 2025 00:00:00 +0000

Confidential computing includes various methods to enhance data security, notably by processing sensitive information within TEE. However, TEE remain vulnerable to SCA, such as cache timing attacks, which exploit timing variations to extract confidential data. Existing TEE designs do not provide sufficient protection against these threats, highlighting the need for stronger security measures. This study focuses on integrating countermeasures specifically targeting timing and cache vulnerabilities within a TEE. The implementation will leverage the RISC-V architecture to explore its potential in mitigating SCA within TEE.

Enhancing Keystone Security Against Cache Timing Attacks: A Modular Approach

Sun, 15 Jun 2025 00:00:00 +0000

Confidential computing includes various methods to enhance data security, notably by processing sensitive information within Trusted Execution Environments (TEEs). However, TEEs remain vulnerable to Side-Channel Attacks (SCAs), such as cache timing attacks, which exploit timing variations to extract confidential data. Existing TEE designs do not provide sufficient protection against these threats, highlighting the need for stronger security measures. This study focuses on integrating countermeasures specifically targeting timing and cache vulnerabilities within a TEE. The implementation will leverage the RISC-V architecture to explore its potential in mitigating SCA within TEE.