CVA6 - Exploring the structure through Vivado
In the context of different projects, I need to explore the architecture of the CVA6 core. Reading through the SystemVerilog code is not no easy, I’d rather like to use Vivado for that.
Vivado scripts
The CVA6 repository (https://github.com/openhwgroup/cva6) proposes a simple Makefile to generate the bitstream. Once prerequisites are installed, a simple make fpga
will generate everything. However, in we open the Vivado project afterwards, it is basically empty.