Reference

• Documentation: http://docs.keystone-enclave.org/en/latest/Getting-Started/Running-Keystone-on-CVA6.html. Based on revision e9fcf7f.

• CVA6 revision f301d69.

Prerequisites

• Vivado 2018.3.

• Genesys2 FPGA board.

Building a CVA6-ready Keystone image

NB: we didn’t enable the root of trust for attestation report yet (http://docs.keystone-enclave.org/en/latest/Getting-Started/Running-Keystone-on-CVA6.html#root-of-trust) as it seems we don’t need it for the moment.

# Cloning the Keystone repository
export KEYSTONE_ROOT=$HOME/keystone
git clone https://github.com/keystone-enclave/keystone.git $KEYSTONE_ROOT
cd $KEYSTONE_ROOT
git checkout e9fcf7f26a788c282647f820393dd262560f60cc
git submodule update --init --recursive

# Building Keystone
KEYSTONE_PLATFORM=cva6 make

# Flashing an SD card
sudo KEYSTONE_PLATFORM=cva6 SD_DEVICE=/dev/sdb make flash

• Be careful of the device ID (/dev/sdb in this tutorial).

export REPO_ROOT=$HOME/keystone
git clone --recurse-submodules https://github.com/keystone-enclave/keystone.git $REPO_ROOT
cd $REPO_ROOT

For a first build of a Buildroot-based image:

make -j$(nproc)

The following command will simply run the Buildroot image in QEmu:

make run

• Login: root

Introduction

In the context of a research project with a PhD student, we have to work on the microarchitecture of a CVA6 and make it compatible with some JIT code (VMIL'23 talk). The official CVA6 repository has recently pushed new scripts to create the SDK. As we already started our work, we want to generate the SDK with the old method on a fork of the CVA6..

Introduction

The idea of this post is to explore how we can add a CSR in the CVA6 processor and how we can check its behavior in GTKwave. In this tutorial, we will try to add a CSR named dmpcfg at address 0x3f0.

Adding a CSR in the CVA6 HDL code

For the CVA6, CSRs are implemented in https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv. In this file, there are two important processes:

• csr_read_process: https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L188, the CSR read logic.
• csr_update: https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L488, the CSR update/write logic.

Update of the write logic

https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L488

Introduction

CVA6 is a processor from the OpenHW Group: 64-bit, Linux-capable and written in SystemVerilog.

Requirements

In order to generate a CVA6 model with export, Verilator must be installed from sources as the Makefile requires a C++ file https://github.com/pcotret/cva6/blob/vcd_patch/Makefile#L551. For this tutorial, Verilator 4.110 was chosen as it is used in the official CI flow.

git clone https://github.com/verilator/verilator
cd verilator
git pull
git checkout v4.110
export VERILATOR_ROOT=`pwd`
autoconf
./configure
make -j$(nproc)

Verilator binaries are generated in <verilator_cloned_repo/bin> and must be added to PATH.

The Rocket Chip is poorly documented. In order to understand the structure of the Scala code, https://github.com/freechipsproject/diagrammer is a tool able to generate Dot diagrams helping to understand what’s inside this processor.

NB: it has been on Debian Bullseye

# Prerequisites, dot interactive viewer
sudo apt install xdot
# Cloning the diagram generation tool
git clone https://github.com/freechipsproject/diagrammer
cd diagrammer
git checkout v1.3.3
./diagram.sh -i freechips.rocketchip.system.DefaultConfig.fir --module-name "Rocket" --just-top-level

Note that the *.fir file is available in the Rocket Chip emulator directory. Arguments: