CVA6 - Exploring the structure through Vivado
In the context of different projects, I need to explore the architecture of the CVA6 core. Reading through the SystemVerilog code is not no easy, I’d rather like to use Vivado for that.
Vivado scripts
The CVA6 repository (https://github.com/openhwgroup/cva6) proposes a simple Makefile to generate the bitstream. Once prerequisites are installed, a simple make fpga will generate everything. However, in we open the Vivado project afterwards, it is basically empty.
The idea is to modify the script which manage Vivado steps to stop right after project creation.
The main script is located at ./corev_apu/fpga/scripts/run.tcl. You just need to comment lines after project creation: the following steps such as bitstream generation will fail but you will keep the initial Vivado project with the CVA6 SoC as the main component.
update_compile_order -fileset sources_1
add_files -fileset constrs_1 -norecurse constraints/$project.xdc
-synth_design -rtl -name rtl_1
+#synth_design -rtl -name rtl_1
-set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
+#set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
-launch_runs synth_1
-wait_on_run synth_1
-open_run synth_1
+#launch_runs synth_1
+#wait_on_run synth_1
+#open_run synth_1
-exec mkdir -p reports/
-exec rm -rf reports/*
+#exec mkdir -p reports/
+#exec rm -rf reports/*
-check_timing -verbose -file reports/$project.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
-report_utilization -hierarchical -file reports/$project.utilization.rpt
-report_cdc -file reports/$project.cdc.rpt
-report_clock_interaction -file reports/$project.clock_interaction.rpt
+#check_timing -verbose -file reports/$project.check_timing.rpt
+#report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/$project.timing_WORST_100.rpt
+#report_timing -nworst 1 -delay_type max -sort_by group -file reports/$project.timing.rpt
+#report_utilization -hierarchical -file reports/$project.utilization.rpt
+#report_cdc -file reports/$project.cdc.rpt
+#report_clock_interaction -file reports/$project.clock_interaction.rpt
# set for RuntimeOptimized implementation
-set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+#set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
+#set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1]
-launch_runs impl_1
-wait_on_run impl_1
-launch_runs impl_1 -to_step write_bitstream
-wait_on_run impl_1
-open_run impl_1
+#launch_runs impl_1
+#wait_on_run impl_1
+#launch_runs impl_1 -to_step write_bitstream
+#wait_on_run impl_1
+#open_run impl_1
# output Verilog netlist + SDC for timing simulation
-write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
-write_verilog -force -mode timesim work-fpga/${project}_timesim.v
-write_sdf -force work-fpga/${project}_timesim.sdf
+#write_verilog -force -mode funcsim work-fpga/${project}_funcsim.v
+#write_verilog -force -mode timesim work-fpga/${project}_timesim.v
+#write_sdf -force work-fpga/${project}_timesim.sdf
# reports
-exec mkdir -p reports/
-exec rm -rf reports/*
-check_timing -file reports/${project}.check_timing.rpt
-report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
-report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
-report_utilization -hierarchical -file reports/${project}.utilization.rpt
+#exec mkdir -p reports/
+#exec rm -rf reports/*
+#check_timing -file reports/${project}.check_timing.rpt
+#report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports/${project}.timing_WORST_100.rpt
+#report_timing -nworst 1 -delay_type max -sort_by group -file reports/${project}.timing.rpt
+#report_utilization -hierarchical -file reports/${project}.utilization.rpt
Vivado synthesis results
If you care about synthesis results of the CPU, Vivado may perform unwanted optimizations. In the synthesis configuration windows, you can set the -flatten_hierarchy flag to none.