Introduction

CVA6 is a processor from the OpenHW Group: 64-bit, Linux-capable and written in SystemVerilog.

Requirements

In order to generate a CVA6 model with export, Verilator must be installed from sources as the Makefile requires a C++ file https://github.com/pcotret/cva6/blob/vcd_patch/Makefile#L551. For this tutorial, Verilator 4.110 was chosen as it is used in the official CI flow.

git clone https://github.com/verilator/verilator
cd verilator
git pull
git checkout v4.110
export VERILATOR_ROOT=`pwd`
autoconf
./configure
make -j$(nproc)

Verilator binaries are generated in <verilator_cloned_repo/bin> and must be added to PATH.

The Rocket Chip is poorly documented. In order to understand the structure of the Scala code, https://github.com/freechipsproject/diagrammer is a tool able to generate Dot diagrams helping to understand what’s inside this processor.

NB: it has been on Debian Bullseye

# Prerequisites, dot interactive viewer
sudo apt install xdot
# Cloning the diagram generation tool
git clone https://github.com/freechipsproject/diagrammer
cd diagrammer
git checkout v1.3.3
./diagram.sh -i freechips.rocketchip.system.DefaultConfig.fir --module-name "Rocket" --just-top-level

Note that the *.fir file is available in the Rocket Chip emulator directory. Arguments:

The idea is to debug a simple program on an emulated Rocket. The procedure is well defined on the officiel Rocket repository. This post basically summarizes the needed steps.

Generating the emulator

Let’s say you have a default rocket-chip repository. You need to add a Remote Bit-Bang client in the emulator by modifying src/main/scala/system/Configs.scala:

@@ -86,3 +86,4 @@ class MMIOPortOnlyConfig extends Config(
 
 class BaseFPGAConfig extends Config(new BaseConfig ++ new WithCoherentBusTopology)
 class DefaultFPGAConfig extends Config(new WithNSmallCores(1) ++ new BaseFPGAConfig)
+class DefaultConfigRBB extends Config(new WithJtagDTMSystem ++ new WithNBigCores(1) ++ new WithCoherentBusTopology ++ new BaseConfig)

Building the emulator

rocket-chip$ cd emulator
emulator$ CONFIG=freechips.rocketchip.system.DefaultConfigRBB make

Compiling a test program

char text[] = "Vafgehpgvba frgf jnag gb or serr!";

// Don't use the stack, because sp isn't set up.
volatile int wait = 1;

int main()
{
    while (wait)
        ;

    // Doesn't actually go on the stack, because there are lots of GPRs.
    int i = 0;
    while (text[i]) {
        char lower = text[i] | 32;
        if (lower >= 'a' && lower <= 'm')
            text[i] += 13;
        else if (lower > 'm' && lower <= 'z')
            text[i] -= 13;
        i++;
    }

    while (!wait)
        ;
}

This C code (which performs a ROT13 transformation) can be saved in a hello_world.c file. In order to compile it, it is assumed to the same settings as for riscv-tests. In this case, it is assumed we modified this C code and that debug symbols were added in the Makefile.

Verilator basics

Basic steps for a simulation of an ALU in Verilator is given in this link.

GTKWave customization

There are two way to customize the GTKWave rendering :

• TCL scripts:
  • https://gist.github.com/pcotret/cfff0b6fe449c308f6e34450c11baaa9
  • https://ughe.github.io/2018/11/13/gtkwave-automation
• gtkwaverc configuration file:
  • Example: https://github.com/gtkwave/gtkwave/blob/master/gtkwave3-gtk3/examples/gtkwaverc

Command

gtkwave -S tcl_script.tcl waveform.vcd 

GTKWave will look for .gtkwaverc in:

Introduction

In the context of a research project related to RIMI [1], we need to add new instructions in the Rocket Chip decoder. @QDucasse already proposed an analysis of the structure of the Rocket Chip source code [1]. This blog post aims to give a bit more details about the instruction encoding for load/store instructions in particular.

Instructions specification

Each instruction is defined with a dictonary of parameters (rocket-chip/IDecode.scala at v1.6 · chipsalliance/rocket-chip · GitHub). Here is a summary for the RVI subset:

Capstone & RISC-V

Just a few notes about playing with Capstone for RISC-V ISA. Be aware that RISC-V support has been added recently in Capstone. If you want to use Python bindings, you must install a v5 release candidate:

pip3 install capstone==5.0-rc2

[1] is an online RISC-V ISA decoder. In the context of a research project, we had to decode instructions with Capstone [2]. Here is a simple example with two instructions (same instruction copied twice):