Verilator basics

Basic steps for a simulation of an ALU in Verilator is given in this link.

GTKWave customization

There are two way to customize the GTKWave rendering :

• TCL scripts:
  • https://gist.github.com/pcotret/cfff0b6fe449c308f6e34450c11baaa9
  • https://ughe.github.io/2018/11/13/gtkwave-automation
• gtkwaverc configuration file:
  • Example: https://github.com/gtkwave/gtkwave/blob/master/gtkwave3-gtk3/examples/gtkwaverc

Command

gtkwave -S tcl_script.tcl waveform.vcd 

GTKWave will look for .gtkwaverc in:

Introduction

In the context of a research project related to RIMI [1], we need to add new instructions in the Rocket Chip decoder. @QDucasse already proposed an analysis of the structure of the Rocket Chip source code [1]. This blog post aims to give a bit more details about the instruction encoding for load/store instructions in particular.

Instructions specification

Each instruction is defined with a dictonary of parameters (rocket-chip/IDecode.scala at v1.6 · chipsalliance/rocket-chip · GitHub). Here is a summary for the RVI subset:

Capstone & RISC-V

Just a few notes about playing with Capstone for RISC-V ISA. Be aware that RISC-V support has been added recently in Capstone. If you want to use Python bindings, you must install a v5 release candidate:

pip3 install capstone==5.0-rc2

[1] is an online RISC-V ISA decoder. In the context of a research project, we had to decode instructions with Capstone [2]. Here is a simple example with two instructions (same instruction copied twice):

Introduction

In the context of a research project related to RIMI [1], we need to add a new CSR (Control & Status Register) in the Rocket processor [2] in order to store new security settings. There are obviously modifications to do in the hardware description of the processor. This blog article tries to sum up what needs to be done.

Hardware stack of the Rocket Chip

The first difficulty with the Rocket Chip is its implementatinon langage, Chisel. It is recommended to learn the basics before going deeper in the Rocket Chip. Some resources:

Introduction

In the context of a research project related to RIMI [1], we need to add a new CSR (Control & Status Register) in the Rocket processor [2] in order to store new security settings. There are obviously modifications to do in the hardware description of the processor (it will be the topic of a future article). However, we also need to modify a few lines of the software stack.

Introduction

Two methods can be done:

• Including the processor code in LiteX framework (see CV32E40P [4]).
• Importing the processor code from an external repository (see FemtoRV [5]).

The choice mainly depends on how the HDL code is written. This tutorial focuses on the first method as targeted processors will be composed of several HDL files. We will see later how it is configured.

LiteX workflow for custom processors

This tutorial is based on the work done by Antmicro for the CV32E40P [4].