Rocket RISC-V processor - Adding custom instructions

Introduction

In the context of a research project related to RIMI [1], we need to add new instructions in the Rocket Chip decoder. @QDucasse already proposed an analysis of the structure of the Rocket Chip source code [1]. This blog post aims to give a bit more details about the instruction encoding for load/store instructions in particular.

Instructions specification

Each instruction is defined with a dictonary of parameters (rocket-chip/IDecode.scala at v1.6 · chipsalliance/rocket-chip · GitHub). Here is a summary for the RVI subset:

For the Rocket Chip, we can see that due to the modular structure of the RISC-V ISA, each subset is a new class which is added or not to the CPU thanks to input parameters.

These parameters can be explained as follows:

Playing with the data width of load/store instructions

Instructions encoding

In order to add an instruction in the Rocket CPU, two things must be done:

• Adding the instruction encoding: example of the LB instruction

• Adding the parameter dictionary values: example fo the LB instruction

The new instruction can be added in an existing dictionary or by creating a new dictionary as in [2]. In this article, let’s say we want to add a custom LR load instruction.

// Instructions.scala
def LB1                = BitPat("b?????????????????000?????0011111")
// IDecode.scala
LB1->       List(Y,N,N,N,N,N,N,Y,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),

Data width for load instructions

Similar assumptions can be made with store instructions.

Load instructions are specified with the same set of parameters rocket-chip/IDecode.scala at dc74f388124704e0838377fe94074175300aff19 · QDucasse/rocket-chip · GitHub. Therefore, how can we find the data width for the load ?

The size is given here

ex_reg_mem_size := Mux(usingHypervisor && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))

val id_inst = id_expanded_inst.map(_.bits) // id_inst is a binary version of the instruction
ex_reg_mem_size := Mux(usingHypervisor && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) // Execute stage: size is given in 13,12 bits of the instruction
mem_reg_mem_size := ex_reg_mem_size // Memory stage: size is transmitted here
wb_reg_mem_size := mem_reg_mem_size // Writeback stage: size is transmitted here

Then, we can confirm by having a look at instruction encoding of load instructions:

• Bits 13 and 12 (low bits of the funct3 field) are different for each load: it specify the data width as shown in previous code snippets.

• Bit 14 is related to unsigned loads:

io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))

References

[1] Rocket chip structure

[2] Adding HW/SW support for the load and store tag instructions · lowRISC: Collaborative open silicon engineering