Adding custom instructions in the RISC-V ISA

The RISC-V instruction set is known to be a modular ISA [risd]: it is usually composed of a common base (RVI, for integers manipulation) and additional extensions (multiplications, compressed instructions, floating numbers…). It also accepts “external” extensions (cryptography [risb], cache handling [risa] or even JIT-related operations [risc]). This tutorial shows how to add a simple instruction to the RVI subset: as a consequence, it will consist of modifications of existing files that are included in all RISC-V ISA combinations (RVI is included by default).

Contents:

• Adding a custom instruction in the RVI subset
  • Custom opcodes
  • Custom instructions in the RISC-V ISA
  • Example of the M extension
  • Example of the cryptography extension
• Custom instruction in the software toolchain
  • RISC-V default toolchain
  • Adding a custom instruction in the cross-compiler
  • Adding a custom instruction in Spike
  • Adding a custom instruction in gem5
  • Simulation of a 32-bit binary with Spike

References

nita

A tutorial on the gem5 minor cpu model. https://nitish2112.github.io/post/gem5-minor-cpu/.

hsa

Adding custom instructions to the risc-v gnu-gcc toolchain. https://hsandid.github.io/posts/risc-v-custom-instruction.

nitb

Adding custom instruction to riscv isa and running it on gem5 and spike. https://nitish2112.github.io/post/adding-instruction-riscv.

risa

Cache management operations for risc-v. https://github.com/riscv/riscv-CMOs.

risb

Risc-v cryptography extension. https://github.com/riscv/riscv-crypto.

risc

Risc-v j extension. https://github.com/riscv/riscv-j-extension.

risd

The RISC-V instruction set manual - volume i: unprivileged isa. https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf.

gema

Gem5 tutorial. http://learning.gem5.org/book/.

gemb

Gem5: learning gem5. https://www.gem5.org/documentation/learning_gem5/introduction/.