Hardware Security for Just-in-Time Compilation in Language Virtual Machines
Work on the RISC-V ISA, extending it for the security of language VMs.
Mar 29, 2024
Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cache
Mar 5, 2024
Cache locking against cache-based side-channel attacks
Feb 8, 2024
Gigue: A JIT Code Binary Generator for Hardware Testing
Oct 23, 2023
Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections
Jul 3, 2023
JIT Compiler Security through Low-Cost RISC-V Extension
May 15, 2023
Porting a JIT compiler to RISC-V: Challenges and Opportunities
Sep 14, 2022
Remarkable Challenges of High-Performance Language Virtual Machines
Feb 1, 2022
Securing a high-level language virtual machine through its ISA: Pharo as a case study
Jun 8, 2021
Engineering degree - Associate professor
Sep 2019
Sep 1, 2019