Pascal Cotret
  • Bio
  • Papers
  • Projects
  • Teaching
  • Publications
    • Enforcing RISC-V TEE Security Against Cache Timing Attacks
    • Security of Dynamically Reconfigurable RISC-V Systems: I/O Attack Focus
    • Support matériel pour la distribution de moteurs IA embarqués
    • War on JITs: Software-Based Attacks and Hybrid Defenses for JIT Compilers - A Comprehensive Survey
    • A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking
    • On The Effect of Replacement Policies on The Security of Randomized Cache Architectures
    • Enhancing Security in Heterogeneous Virtualized Systems: A Focus on I/O Attacks in the existence of IOMMU in a RISC-V architecture
    • RISC-V Embedded AI for IDS Applications
    • Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cache
    • Cache locking against cache-based side-channel attacks
    • Gigue: A JIT Code Binary Generator for Hardware Testing
    • Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections
    • JIT Compiler Security through Low-Cost RISC-V Extension
    • Porting a JIT compiler to RISC-V: Challenges and Opportunities
    • Remarkable Challenges of High-Performance Language Virtual Machines
    • Securing a high-level language virtual machine through its ISA: Pharo as a case study
    • Benchmarking quantized neural networks on FPGAs with FINN
    • Dis, c’est quoi là haut dans le ciel ? C’est un Linux, mon petit
    • A novel lightweight hardware-assisted static instrumentation approach for ARM SoC using debug components
    • A MIPS-based coprocessor for information flow tracking in ARM SoCs
    • Monitoring information flows in heterogeneous SoCs with a dedicated coprocessor
    • Monitoring program execution (and more) on ARM processors
    • ARMHEx: A hardware extension for DIFT on ARM-based SoCs
    • A framework for efficient DIFT in real-world SoCs
    • ARMHEx: a hardware extension for information flow tracking on ARM-based platforms
    • DroneJack: kiss your drones goodbye !
    • ARMHEx: a hardware extension for information flow tracking on ARM-based platforms
    • Pwning ARM Debug Components for Sec-Related Stuff
    • Hit the KeyJack: stealing data from your daily wireless devices incognito
    • Multi-standard OFDM transceiver for heterogeneous system-on-chips
    • Towards a hardware-assisted information flow tracking ecosystem for ARM processors
    • A hardware coprocessor for Zynq-based Dynamic Information Flow Tracking
    • A portable approach for SoC-based Dynamic Information Flow Tracking implementations
    • Protection of heterogeneous architectures on FPGAs: an approach based on hardware firewalls
    • Embedded wavelet-based face recognition under variable position
    • HardBlare: an efficient hardware-assisted DIFC for non-modified embedded processors
    • Reconnaissance faciale basée sur les ondelettes robuste et optimisée pour les systèmes embarqués
    • Protection des architectures hétérogènes sur FPGA : une approche par pare-feux matériels
    • Protection des architectures hétérogènes multiprocesseurs dans les systèmes embarqués. Une approche décentralisée basée sur des pare-feux matériels
    • Lightweight reconfiguration security services for AXI-based MPSoCs
    • Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system
    • Self-reconfigurable security-enhanced communications in FPGA-based MPSoCs
    • Self-configuration of latency-efficient security enhancements for mpsoc communications monitoring
    • Bus-based MPSoC security through communication protection: A latency-efficient alternative
    • Efficient key-dependent message authentication in reconfigurable hardware
    • Protecting communications in bus-based MPSoCs using hardware firewalls
    • Distributed security for communications and memories in a multiprocessor architecture
    • Security Trends for FPGAs
    • HCrypt: A novel concept of crypto-processor with secured key management
    • Secured communications within a multi-processors architecture
    • Sécurisation des communications dans une architecture multi-processeurs
  • Projects
    • SCRATCHS
    • Hardware Security for Just-in-Time Compilation in Language Virtual Machines
    • HardBlare
  • Projects
  • Experience
  • Teaching
    • Apprentice degree - Associate professor and responsible of this degree
    • Engineering degree - Associate professor
    • Cybersecurity of maritime and port systems - post-master degree
  • Researches
    • PhD students
    • Projects list

Enforcing RISC-V TEE Security Against Cache Timing Attacks

Jun 15, 2025·
Oussama Elmnaouri
Pascal Cotret
Pascal Cotret
,
Vianney Lapôtre
,
Loïc Lagadec
· 0 min read
PDF
Type
Speech
Publication
In International Workshops on Cryptographic architectures embedded in logic devices
Last updated on Jun 15, 2025
Riscv Security Hardware
Pascal Cotret
Authors
Pascal Cotret
Associate Professor
Security of Dynamically Reconfigurable RISC-V Systems: I/O Attack Focus Jun 3, 2025 →

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