Publications

(2024). A Fine-Grained Dynamic Partitioning Against Cache-Based Timing Attacks via Cache Locking. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024.
(2024). Enhancing Security in Heterogeneous Virtualized Systems: A Focus on I/O Attacks in the existence of IOMMU in a RISC-V architecture. In GDR SoC².
(2024). RISC-V Embedded AI for IDS Applications. In RESSI 2024 Rendez-vous de la Recherche et de l’Enseignement de la Sécurité des Systèmes d’Information.
(2024). Verrouillage des lignes de cache pour la lutte contre les attaques par canaux auxiliaires exploitant les mémoires cache. In 1ère conférence française annuelle dédiée à la cyber embarquée et à son écosystème (CyberOnBoard 2024).
(2024). Cache locking against cache-based side-channel attacks. In Ecole d’hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH).
(2023). Gigue: A JIT Code Binary Generator for Hardware Testing. In 2023 Workshop on Virtual Machines and Language Implementations.
(2023). Work in Progress: Thwarting Timing Attacks in Microcontrollers using Fine-grained Hardware Protections. In SILM - IEEE Euro S&P workshop.
(2023). JIT Compiler Security through Low-Cost RISC-V Extension. In RAW - 30th Reconfigurable Architectures Workshop.
(2022). Porting a JIT compiler to RISC-V: Challenges and Opportunities. In MPLR - Managed Programming Languages and Runtimes 2022.
(2022). Remarkable Challenges of High-Performance Language Virtual Machines. In Research Report Inria Lille - Nord Europe.